FM / asm

/usr/include/powerpc64-linux-gnu/asm

Name	Size	Mode	Actions
auxvec.h	1846	0644	edit dl rm
bitsperlong.h	312	0644	edit dl rm
bootx.h	4401	0644	edit dl rm
bpf_perf_event.h	40	0644	edit dl rm
byteorder.h	550	0644	edit dl rm
cputable.h	2384	0644	edit dl rm
eeh.h	2233	0644	edit dl rm
elf.h	13400	0644	edit dl rm
epapr_hcalls.h	4259	0644	edit dl rm
errno.h	278	0644	edit dl rm
fcntl.h	367	0644	edit dl rm
ioctl.h	302	0644	edit dl rm
ioctls.h	4363	0644	edit dl rm
ipcbuf.h	1057	0644	edit dl rm
kvm.h	26122	0644	edit dl rm
kvm_para.h	2778	0644	edit dl rm
mman.h	1279	0644	edit dl rm
msgbuf.h	1159	0644	edit dl rm
nvram.h	2062	0644	edit dl rm
opal-prd.h	1767	0644	edit dl rm
papr-miscdev.h	184	0644	edit dl rm
papr-sysparm.h	2057	0644	edit dl rm
papr-vpd.h	538	0644	edit dl rm
param.h	31	0644	edit dl rm
perf_event.h	550	0644	edit dl rm
perf_regs.h	2748	0644	edit dl rm
poll.h	30	0644	edit dl rm
posix_types.h	594	0644	edit dl rm
ps3fb.h	1781	0644	edit dl rm
ptrace.h	7725	0644	edit dl rm
resource.h	34	0644	edit dl rm
sembuf.h	1144	0644	edit dl rm
setup.h	188	0644	edit dl rm
shmbuf.h	1723	0644	edit dl rm
sigcontext.h	4344	0644	edit dl rm
siginfo.h	33	0644	edit dl rm
signal.h	2547	0644	edit dl rm
socket.h	600	0644	edit dl rm
sockios.h	33	0644	edit dl rm
spu_info.h	774	0644	edit dl rm
stat.h	2362	0644	edit dl rm
statfs.h	32	0644	edit dl rm
swab.h	560	0644	edit dl rm
termbits.h	4104	0644	edit dl rm
termios.h	1697	0644	edit dl rm
tm.h	734	0644	edit dl rm
types.h	1304	0644	edit dl rm
ucontext.h	961	0644	edit dl rm
unistd.h	562	0644	edit dl rm
unistd_32.h	12065	0644	edit dl rm
unistd_64.h	11149	0644	edit dl rm
vas-api.h	649	0644	edit dl rm

Edit: /usr/lib/linux/uapi/powerpc/asm/auxvec.h (1846B)

/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef _ASM_POWERPC_AUXVEC_H
#define _ASM_POWERPC_AUXVEC_H

/*
 * We need to put in some extra aux table entries to tell glibc what
 * the cache block size is, so it can use the dcbz instruction safely.
 */
#define AT_DCACHEBSIZE		19
#define AT_ICACHEBSIZE		20
#define AT_UCACHEBSIZE		21
/* A special ignored type value for PPC, for glibc compatibility.  */
#define AT_IGNOREPPC		22

/* The vDSO location. We have to use the same value as x86 for glibc's
 * sake :-)
 */
#define AT_SYSINFO_EHDR		33

/*
 * AT_*CACHEBSIZE above represent the cache *block* size which is
 * the size that is affected by the cache management instructions.
 *
 * It doesn't nececssarily matches the cache *line* size which is
 * more of a performance tuning hint. Additionally the latter can
 * be different for the different cache levels.
 *
 * The set of entries below represent more extensive information
 * about the caches, in the form of two entry per cache type,
 * one entry containing the cache size in bytes, and the other
 * containing the cache line size in bytes in the bottom 16 bits
 * and the cache associativity in the next 16 bits.
 *
 * The associativity is such that if N is the 16-bit value, the
 * cache is N way set associative. A value if 0xffff means fully
 * associative, a value of 1 means directly mapped.
 *
 * For all these fields, a value of 0 means that the information
 * is not known.
 */

#define AT_L1I_CACHESIZE	40
#define AT_L1I_CACHEGEOMETRY	41
#define AT_L1D_CACHESIZE	42
#define AT_L1D_CACHEGEOMETRY	43
#define AT_L2_CACHESIZE		44
#define AT_L2_CACHEGEOMETRY	45
#define AT_L3_CACHESIZE		46
#define AT_L3_CACHEGEOMETRY	47

#define AT_MINSIGSTKSZ		51      /* stack needed for signal delivery */

#define AT_VECTOR_SIZE_ARCH	15 /* entries in ARCH_DLINFO */

#endif

/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_POWERPC_AUXVEC_H #define _ASM_POWERPC_AUXVEC_H /* * We need to put in some extra aux table entries to tell glibc what * the cache block size is, so it can use the dcbz instruction safely. */ #define AT_DCACHEBSIZE 19 #define AT_ICACHEBSIZE 20 #define AT_UCACHEBSIZE 21 /* A special ignored type value for PPC, for glibc compatibility. */ #define AT_IGNOREPPC 22 /* The vDSO location. We have to use the same value as x86 for glibc's * sake :-) */ #define AT_SYSINFO_EHDR 33 /* * AT_*CACHEBSIZE above represent the cache *block* size which is * the size that is affected by the cache management instructions. * * It doesn't nececssarily matches the cache *line* size which is * more of a performance tuning hint. Additionally the latter can * be different for the different cache levels. * * The set of entries below represent more extensive information * about the caches, in the form of two entry per cache type, * one entry containing the cache size in bytes, and the other * containing the cache line size in bytes in the bottom 16 bits * and the cache associativity in the next 16 bits. * * The associativity is such that if N is the 16-bit value, the * cache is N way set associative. A value if 0xffff means fully * associative, a value of 1 means directly mapped. * * For all these fields, a value of 0 means that the information * is not known. */ #define AT_L1I_CACHESIZE 40 #define AT_L1I_CACHEGEOMETRY 41 #define AT_L1D_CACHESIZE 42 #define AT_L1D_CACHEGEOMETRY 43 #define AT_L2_CACHESIZE 44 #define AT_L2_CACHEGEOMETRY 45 #define AT_L3_CACHESIZE 46 #define AT_L3_CACHEGEOMETRY 47 #define AT_MINSIGSTKSZ 51 /* stack needed for signal delivery */ #define AT_VECTOR_SIZE_ARCH 15 /* entries in ARCH_DLINFO */ #endif