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/usr/include/powerpc64-linux-gnu/asm

Name	Size	Mode	Actions
auxvec.h	1846	0644	edit dl rm
bitsperlong.h	312	0644	edit dl rm
bootx.h	4401	0644	edit dl rm
bpf_perf_event.h	40	0644	edit dl rm
byteorder.h	550	0644	edit dl rm
cputable.h	2384	0644	edit dl rm
eeh.h	2233	0644	edit dl rm
elf.h	13400	0644	edit dl rm
epapr_hcalls.h	4259	0644	edit dl rm
errno.h	278	0644	edit dl rm
fcntl.h	367	0644	edit dl rm
ioctl.h	302	0644	edit dl rm
ioctls.h	4363	0644	edit dl rm
ipcbuf.h	1057	0644	edit dl rm
kvm.h	26122	0644	edit dl rm
kvm_para.h	2778	0644	edit dl rm
mman.h	1279	0644	edit dl rm
msgbuf.h	1159	0644	edit dl rm
nvram.h	2062	0644	edit dl rm
opal-prd.h	1767	0644	edit dl rm
papr-miscdev.h	184	0644	edit dl rm
papr-sysparm.h	2057	0644	edit dl rm
papr-vpd.h	538	0644	edit dl rm
param.h	31	0644	edit dl rm
perf_event.h	550	0644	edit dl rm
perf_regs.h	2748	0644	edit dl rm
poll.h	30	0644	edit dl rm
posix_types.h	594	0644	edit dl rm
ps3fb.h	1781	0644	edit dl rm
ptrace.h	7725	0644	edit dl rm
resource.h	34	0644	edit dl rm
sembuf.h	1144	0644	edit dl rm
setup.h	188	0644	edit dl rm
shmbuf.h	1723	0644	edit dl rm
sigcontext.h	4344	0644	edit dl rm
siginfo.h	33	0644	edit dl rm
signal.h	2547	0644	edit dl rm
socket.h	600	0644	edit dl rm
sockios.h	33	0644	edit dl rm
spu_info.h	774	0644	edit dl rm
stat.h	2362	0644	edit dl rm
statfs.h	32	0644	edit dl rm
swab.h	560	0644	edit dl rm
termbits.h	4104	0644	edit dl rm
termios.h	1697	0644	edit dl rm
tm.h	734	0644	edit dl rm
types.h	1304	0644	edit dl rm
ucontext.h	961	0644	edit dl rm
unistd.h	562	0644	edit dl rm
unistd_32.h	12065	0644	edit dl rm
unistd_64.h	11149	0644	edit dl rm
vas-api.h	649	0644	edit dl rm

Edit: /usr/lib/linux/uapi/powerpc/asm/perf_regs.h (2748B)

/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef _ASM_POWERPC_PERF_REGS_H
#define _ASM_POWERPC_PERF_REGS_H

enum perf_event_powerpc_regs {
	PERF_REG_POWERPC_R0,
	PERF_REG_POWERPC_R1,
	PERF_REG_POWERPC_R2,
	PERF_REG_POWERPC_R3,
	PERF_REG_POWERPC_R4,
	PERF_REG_POWERPC_R5,
	PERF_REG_POWERPC_R6,
	PERF_REG_POWERPC_R7,
	PERF_REG_POWERPC_R8,
	PERF_REG_POWERPC_R9,
	PERF_REG_POWERPC_R10,
	PERF_REG_POWERPC_R11,
	PERF_REG_POWERPC_R12,
	PERF_REG_POWERPC_R13,
	PERF_REG_POWERPC_R14,
	PERF_REG_POWERPC_R15,
	PERF_REG_POWERPC_R16,
	PERF_REG_POWERPC_R17,
	PERF_REG_POWERPC_R18,
	PERF_REG_POWERPC_R19,
	PERF_REG_POWERPC_R20,
	PERF_REG_POWERPC_R21,
	PERF_REG_POWERPC_R22,
	PERF_REG_POWERPC_R23,
	PERF_REG_POWERPC_R24,
	PERF_REG_POWERPC_R25,
	PERF_REG_POWERPC_R26,
	PERF_REG_POWERPC_R27,
	PERF_REG_POWERPC_R28,
	PERF_REG_POWERPC_R29,
	PERF_REG_POWERPC_R30,
	PERF_REG_POWERPC_R31,
	PERF_REG_POWERPC_NIP,
	PERF_REG_POWERPC_MSR,
	PERF_REG_POWERPC_ORIG_R3,
	PERF_REG_POWERPC_CTR,
	PERF_REG_POWERPC_LINK,
	PERF_REG_POWERPC_XER,
	PERF_REG_POWERPC_CCR,
	PERF_REG_POWERPC_SOFTE,
	PERF_REG_POWERPC_TRAP,
	PERF_REG_POWERPC_DAR,
	PERF_REG_POWERPC_DSISR,
	PERF_REG_POWERPC_SIER,
	PERF_REG_POWERPC_MMCRA,
	/* Extended registers */
	PERF_REG_POWERPC_MMCR0,
	PERF_REG_POWERPC_MMCR1,
	PERF_REG_POWERPC_MMCR2,
	PERF_REG_POWERPC_MMCR3,
	PERF_REG_POWERPC_SIER2,
	PERF_REG_POWERPC_SIER3,
	PERF_REG_POWERPC_PMC1,
	PERF_REG_POWERPC_PMC2,
	PERF_REG_POWERPC_PMC3,
	PERF_REG_POWERPC_PMC4,
	PERF_REG_POWERPC_PMC5,
	PERF_REG_POWERPC_PMC6,
	PERF_REG_POWERPC_SDAR,
	PERF_REG_POWERPC_SIAR,
	/* Max mask value for interrupt regs w/o extended regs */
	PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1,
	/* Max mask value for interrupt regs including extended regs */
	PERF_REG_EXTENDED_MAX = PERF_REG_POWERPC_SIAR + 1,
};

#define PERF_REG_PMU_MASK	((1ULL << PERF_REG_POWERPC_MAX) - 1)

/*
 * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300
 * includes 11 SPRS from MMCR0 to SIAR excluding the
 * unsupported SPRS MMCR3, SIER2 and SIER3.
 */
#define PERF_REG_PMU_MASK_300	\
	((1ULL << PERF_REG_POWERPC_MMCR0) | (1ULL << PERF_REG_POWERPC_MMCR1) | \
	(1ULL << PERF_REG_POWERPC_MMCR2) | (1ULL << PERF_REG_POWERPC_PMC1) | \
	(1ULL << PERF_REG_POWERPC_PMC2) | (1ULL << PERF_REG_POWERPC_PMC3) | \
	(1ULL << PERF_REG_POWERPC_PMC4) | (1ULL << PERF_REG_POWERPC_PMC5) | \
	(1ULL << PERF_REG_POWERPC_PMC6) | (1ULL << PERF_REG_POWERPC_SDAR) | \
	(1ULL << PERF_REG_POWERPC_SIAR))

/*
 * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31
 * includes 14 SPRs from MMCR0 to SIAR.
 */
#define PERF_REG_PMU_MASK_31	\
	(PERF_REG_PMU_MASK_300 | (1ULL << PERF_REG_POWERPC_MMCR3) | \
	(1ULL << PERF_REG_POWERPC_SIER2) | (1ULL << PERF_REG_POWERPC_SIER3))

#endif /* _ASM_POWERPC_PERF_REGS_H */

/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_POWERPC_PERF_REGS_H #define _ASM_POWERPC_PERF_REGS_H enum perf_event_powerpc_regs { PERF_REG_POWERPC_R0, PERF_REG_POWERPC_R1, PERF_REG_POWERPC_R2, PERF_REG_POWERPC_R3, PERF_REG_POWERPC_R4, PERF_REG_POWERPC_R5, PERF_REG_POWERPC_R6, PERF_REG_POWERPC_R7, PERF_REG_POWERPC_R8, PERF_REG_POWERPC_R9, PERF_REG_POWERPC_R10, PERF_REG_POWERPC_R11, PERF_REG_POWERPC_R12, PERF_REG_POWERPC_R13, PERF_REG_POWERPC_R14, PERF_REG_POWERPC_R15, PERF_REG_POWERPC_R16, PERF_REG_POWERPC_R17, PERF_REG_POWERPC_R18, PERF_REG_POWERPC_R19, PERF_REG_POWERPC_R20, PERF_REG_POWERPC_R21, PERF_REG_POWERPC_R22, PERF_REG_POWERPC_R23, PERF_REG_POWERPC_R24, PERF_REG_POWERPC_R25, PERF_REG_POWERPC_R26, PERF_REG_POWERPC_R27, PERF_REG_POWERPC_R28, PERF_REG_POWERPC_R29, PERF_REG_POWERPC_R30, PERF_REG_POWERPC_R31, PERF_REG_POWERPC_NIP, PERF_REG_POWERPC_MSR, PERF_REG_POWERPC_ORIG_R3, PERF_REG_POWERPC_CTR, PERF_REG_POWERPC_LINK, PERF_REG_POWERPC_XER, PERF_REG_POWERPC_CCR, PERF_REG_POWERPC_SOFTE, PERF_REG_POWERPC_TRAP, PERF_REG_POWERPC_DAR, PERF_REG_POWERPC_DSISR, PERF_REG_POWERPC_SIER, PERF_REG_POWERPC_MMCRA, /* Extended registers */ PERF_REG_POWERPC_MMCR0, PERF_REG_POWERPC_MMCR1, PERF_REG_POWERPC_MMCR2, PERF_REG_POWERPC_MMCR3, PERF_REG_POWERPC_SIER2, PERF_REG_POWERPC_SIER3, PERF_REG_POWERPC_PMC1, PERF_REG_POWERPC_PMC2, PERF_REG_POWERPC_PMC3, PERF_REG_POWERPC_PMC4, PERF_REG_POWERPC_PMC5, PERF_REG_POWERPC_PMC6, PERF_REG_POWERPC_SDAR, PERF_REG_POWERPC_SIAR, /* Max mask value for interrupt regs w/o extended regs */ PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1, /* Max mask value for interrupt regs including extended regs */ PERF_REG_EXTENDED_MAX = PERF_REG_POWERPC_SIAR + 1, }; #define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1) /* * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 * includes 11 SPRS from MMCR0 to SIAR excluding the * unsupported SPRS MMCR3, SIER2 and SIER3. */ #define PERF_REG_PMU_MASK_300 \ ((1ULL << PERF_REG_POWERPC_MMCR0) | (1ULL << PERF_REG_POWERPC_MMCR1) | \ (1ULL << PERF_REG_POWERPC_MMCR2) | (1ULL << PERF_REG_POWERPC_PMC1) | \ (1ULL << PERF_REG_POWERPC_PMC2) | (1ULL << PERF_REG_POWERPC_PMC3) | \ (1ULL << PERF_REG_POWERPC_PMC4) | (1ULL << PERF_REG_POWERPC_PMC5) | \ (1ULL << PERF_REG_POWERPC_PMC6) | (1ULL << PERF_REG_POWERPC_SDAR) | \ (1ULL << PERF_REG_POWERPC_SIAR)) /* * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31 * includes 14 SPRs from MMCR0 to SIAR. */ #define PERF_REG_PMU_MASK_31 \ (PERF_REG_PMU_MASK_300 | (1ULL << PERF_REG_POWERPC_MMCR3) | \ (1ULL << PERF_REG_POWERPC_SIER2) | (1ULL << PERF_REG_POWERPC_SIER3)) #endif /* _ASM_POWERPC_PERF_REGS_H */